This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-067823, filed Mar. 15, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory device, and, more particularly, to a memory cell array structure of a nonvolatile semiconductor memory which has memory transistors with gate electrodes of a double-layer stacked structure and a method of fabricating the same. Those semiconductor memory device and method are adapted to a NAND type EEPROM (Electrically Erasable and Programmable ROM).
A conventional method of fabricating memory cells will be described below referring to FIGS. 1A through 1G.
A gate oxide film 101 of SiO2 is formed 8 nm thick on the flat-finished major surface of a substrate 100 of, for example, p type silicon, and a first conductive polycrystalline silicon film 102 is formed 100 nm thick on this gate oxide film 101. Then is formed a silicon nitride film (SiN) 103 with a thickness of 150 nm as an etching mask to remove the first polycrystalline silicon film 102 (FIG. 1A).
Next, a photoresist is coated on the entire surface of the silicon nitride film 103 and is then processed by photolithography, thus forming a resist pattern 104. With the resist pattern 104 as a mask, the silicon nitride film 103 is patterned to be an etching mask by anisotropic dry etching such as RIE (Reactive Ion Etching) (FIG. 1B).
Then, the resist pattern 104 is removed by wet etching. Next, with the patterned silicon nitride film 103 used as a mask, the first polycrystalline silicon film 102, the gate oxide film 101 and the semiconductor substrate 100 are selectively etched to a desired depth by anisotropic dry etching. This forms trenches 105 that surround device regions (FIG. 1C).
Then, a post-RIE oxide film 106 is formed 10 nm thick in order to recover from the damages on the etched side of the gate oxide film 101 and the etched surface of the semiconductor substrate 100 (FIG. 1D).
Next, a buried insulating film 107 of SiO2 or the like is formed 600 nm thick on the entire surface of the semiconductor substrate 100 to bury the trenches 105 between the first polycrystalline silicon film 102. The buried insulating film 107 is then planarized to the desired height by CMP (Chemical Mechanical Polishing), thus exposing the silicon nitride film 103 (FIG. 1E).
Thereafter, the silicon nitride film 103 is removed by wet etching, forming device isolation regions comprising the buried insulating film 107 (FIG. 1F).
Then, an ONO film (SiO2xe2x80x94SiNxe2x80x94SiO2) 108 is deposited 12 nm thick on the entire surfaces of the first polycrystalline silicon film 102 and the buried insulating film 107. Thereafter, a second polycrystalline silicon film 109 and a high-melting-point or refractory metal silicide film 110 of Ti, W or the like are deposited in order on this ONO film 108 (FIG. 1G).
Thereafter, to form word lines (WL), the refractory metal silicide film 110, the second polycrystalline silicon film 109, the ONO film 108 and the first polycrystalline silicon film 102 are processed in order by anisotropic dry etching. Then, ion implantation is carried out to form source/drain regions in the semiconductor substrate 100 by which memory cells are completed.
In the case where a memory cell array whose electrodes have such a double-layer stacked structure is adapted to a nonvolatile semiconductor memory (e.g., EEPROM), if the post-RIE oxide film 106 is a thermal oxide film, the gate size varies depending on the oxidation rate. That is, as the oxidation rate of the first polycrystalline silicon film 102 is fast with respect to the semiconductor substrate 100, the edge portions of the electrodes are cut back from (come inside) the edge portions of the device regions (FIG. 1G).
In general, an EEPROM has a floating gate electrically isolated from the peripheral sections and stores data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d by injecting or discharging electrons into or from the floating gate. When a high electric field of about 10 MV/cm is applied to both ends of the silicon oxide film, a tunnel current of the order of 10xe2x88x9210 A/xcexcm2 flows. This current is called FN (Fowler-Nordheim) current.
Injection of electrons (writing) is implemented by applying a high voltage of 20V to a control gate (CG) and setting the source/drain region of the semiconductor substrate to 0V as shown in FIG. 2A. Under this situation, a floating gate (FG) has a high potential and a high electric field is applied to the gate oxide film, so that the FN current flows to the source/drain region from the floating gate (FG). As electrons travel in the opposite direction to that of the current, electrons are injected into the floating gate (FG).
In discharging (erasing) electrons from the floating gate (FG), as shown in FIG. 2B, 0V is applied to the control gate (CG) and 20V to the drain region. Under this situation, a high electric field is generated toward the floating gate (FG) from the drain region. As a result, the FN current flows to the floating gate (FG) from the drain region and electrons are discharged from the floating gate (FG).
As shown in FIG. 2C, a strong electric field is applied to the gate oxide film at the portion where the end portion of the floating gate on which the electric field concentrates in this operation faces the source/drain region, thereby damaging the gate oxide film.
Even in the write operation of the nonvolatile memory in FIG. 1G, electrons are injected into the first polycrystalline silicon film 102, so that the voltage of about 20V applied to the refractory metal silicide film 110 produces the FN current in the gate oxide film 101.
To discharge electrons from the first polycrystalline silicon film 102 in the erasing operation of the nonvolatile memory, a voltage of about 20V is applied to the semiconductor substrate 100. With the state-of-the-art technology, writing to memory cells block by block and simultaneous erasing, which respectively take several xcexcsec and several msec, are carried out to make writing and erasing faster.
As apparent from this, erasure takes longer time than writing. If the edge of each gate electrode is located on the semiconductor substrate 100 at an area equivalent to the cathode electrode in erase mode, an electric field concentrates on this area, causing the edge portion to have a higher current density than that of the flat surface as implied above referring to FIG. 2C.
The higher the current density of the FN current becomes, the larger the trap is formed in the gate oxide film. This leads to a variation in threshold voltage even at the stage of fewer writing and erasing cycles.
Accordingly, it is an object of the present invention to provide a semiconductor memory device having a gate structure which prevents an electric field from concentrating on the widthwise edge portion of gate electrodes in order to reduce charges produced in an oxide film by electric stress, and a method of fabricating the same.
This invention provides memory cells having transistors which are so designed to prevent an electric field from concentrating on the widthwise edge portion of gate electrodes in order to reduce charges produced in an oxide film by electric stress. This structure can permit an electric field to be uniformly distributed over the gate electrodes and can thus contribute to fabricating stable memory transistors whose threshold voltage (Vth) has a less variation.
To achieve the above object, according to the first aspect of this invention, there is provided a semiconductor memory device comprising a semiconductor substrate having a major surface; a device region formed on the major surface of the semiconductor substrate; a device isolation region, formed by burying an insulating film in a trench formed in the major surface of the semiconductor substrate, for surrounding and defining the device region; a gate insulating film formed on the semiconductor substrate in the device region; and a first gate electrode formed on the gate insulating film in contact therewith, widthwise end portions of the first gate electrode extending at least over the device isolation region.
It is desirable that the first gate electrode is formed of polysilicon.
It is desirable to dope nitrogen atoms in those areas of the first gate electrode which extend at least over the device isolation region.
It is desirable that the first gate electrode is formed of polysilicon, and 3 to 5 wt % inclusive of nitrogen atoms are doped in those areas of the first gate electrode which extend at least over the device isolation region.
Nitrogen atoms may be doped in the first gate electrode almost evenly.
It is desirable that the first gate electrode is formed of polysilicon in which 3 to 5 wt % inclusive of nitrogen atoms are doped almost evenly.
The semiconductor memory device may further comprise a second gate electrode formed on the first gate electrode via an inter-electrode insulating film.
According to the second aspect of this invention, there is provided a method of fabricating a semiconductor memory device that comprises the steps of preparing a semiconductor substrate having a major surface on which device regions having source/drain regions formed therein and device isolation regions for defining the device regions are formed; depositing a gate insulating film, a polysilicon film and an inter-electrode insulating film in order on the major surface of the semiconductor substrate; patterning the polysilicon film into a plurality of first gate electrodes by etching the inter-electrode insulating film, the polysilicon film and the gate insulating film in a predetermined shape; forming trenches among the plurality of first gate electrodes by etching the major surface of the semiconductor substrate correspondingly to the device isolation regions; doping nitrogen atoms into exposed surfaces of the first gate electrodes; and performing a post oxidation treatment for recovery from damages in the trenches of the semiconductor substrate and on a side of the inter-electrode insulating film.
It is desirable that the step of doping nitrogen atoms into the exposed surfaces of the first gate electrodes includes a step of doping 3 to 5 wt % inclusive of nitrogen atoms.
According to the third aspect of this invention, there is provided a method of fabricating a semiconductor memory device that comprises the steps of preparing a semiconductor substrate having a major surface on which device regions having source/drain regions formed therein and device isolation regions for defining the device regions are formed; depositing a gate insulating film, a polysilicon film doped with nitrogen atoms and an inter-electrode insulating film in order on the major surface of the semiconductor substrate; patterning the polysilicon film into a plurality of first gate electrodes by etching the inter-electrode insulating film, the polysilicon film and the gate insulating film in a predetermined shape; forming trenches among the plurality of first gate electrodes by etching the major surface of the semiconductor substrate correspondingly to the device isolation regions; and performing a post oxidation treatment for recovery from damages in the trenches of the semiconductor substrate and on a side of the inter-electrode insulating film.
It is desirable that the step of forming the polysilicon doped with nitrogen atoms includes a step of doping 3 to 5 wt % inclusive of nitrogen atoms.
In the second and third aspects of this invention, the method may further comprise the step of forming second gate electrodes on the first gate electrodes via the inter-electrode insulating film.
According to this invention, a variation in the threshold voltage of memory cells in the operation of the device can be made smaller by providing nitrogen-doped regions on the sides of the gate electrodes or using a nitrogen-doped polysilicon film. It is therefore possible to provide a highly reliable nonvolatile semiconductor memory device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.